Method and apparatus for testing a non-standard memory device under actual operating conditions

ABSTRACT

A method and apparatus for testing memory devices under actual operating conditions can accommodate non-standard memory devices through the use of an interface board that adapts a non-standard pin configuration to a standard pin configuration on a test substrate. The interface board can include a first surface on which to mount the non-standard device, a pin matching circuit, and a second surface constructed and arranged to couple the pin matching circuit to a standard pin configuration. The interface board can be mounted directly on the test substrate, or coupled to the test substrate through various arrangements of sockets, connection boards, and supports.

[0001] This application claims priority from Korean patent applicationNo. 2001-87064 filed Dec. 28, 2001 in the name of Samsung ElectronicsCo., Ltd., which is herein incorporated by reference; this applicationis a continuation-in-part of U.S. patent application Ser. No. 09/733,336filed Dec. 8, 2000, incorporated by reference.

BACKGROUND

[0002] The present invention relates to test technology forsemiconductor devices, and more particularly, to a method and apparatusfor testing non-standard memory devices under actual operatingconditions.

[0003]FIG. 1 illustrates a conventional process for fabricating andtesting semiconductor integrated circuit (IC) devices and a printedcircuit board onto which the IC devices are assembled. First, numeroussemiconductor devices are fabricated in a semiconductor wafer 10. Thesemiconductor devices are tested at the wafer-level, and faulty devicesare selectively marked for disposal during a sorting process. Non-faultydevices are then separated from the wafer.

[0004] The individual semiconductor devices that pass the wafer-leveltest are then assembled into packages. The packaged devices 20 aretested at the package-level by using a burn-in test, which screens outearly defects under extreme temperature and electrical conditions, and afunctional test, which determines the electrical characteristics of thedevices. Good devices that pass the package-level tests are assembledinto printed circuit board-type products (such as memory module 30 shownin FIG. 1). The board-type products are also tested after assembly.

[0005] A disadvantage of the conventional test process described aboveis that test conditions do not always correspond to actual operatingconditions that the semiconductor devices encounter during actual use.Therefore, even if a packaged device passes the burn-in and thefunctional tests, there might exist some defects that cannot be detecteduntil the device is assembled into the board-type product. Thisincreases production costs due to the expense associated with repairingand retesting the product or, if repair is not possible, with scrappingthe product.

[0006] For example, a large number of semiconductor memory devices areassembled into a board-type memory module such as a Single Inline MemoryModule (SIMM) or a Dual Inline Memory Module (DIMM). Such memory modulesare typically installed onto a system-level board such as themotherboard of a computer system. Even if the module contains only onememory device that does not operate properly after installation, theentire module must be disposed of because it is prohibitively expensiveto remove and replace the improperly operating device which is solderedonto the module.

[0007] Another drawback of the conventional test process is thatconventional test equipment is complicated, bulky and expensive.Manufacturers of semiconductor memory devices typically utilize testerssuch as the Hewlett Packard model HP83000 tester and the Advan tester totest the packaged devices. These testers generate test signal patternsthat simulate memory bus signals (e.g., clock, row address strobe (RAS),column address strobe (CAS), data and address signals) which the memorydevice will receive from a central processing unit (CPU) or chipset whenutilized in the system level board. The test signals are applied to theterminal leads of the memory device under test (DUT), and then thetester analyzes signals received back from the memory device todetermine whether the electrical characteristics are acceptable.Although this type of tester is very flexible and therefore capable of abroad range of tests, it cannot provide an environment identical to thatencountered during actual operation. Furthermore, to provide this testflexibility, the tester becomes more complicated, and thereby moredifficult and more expensive to operate and program.

[0008] To provide a more realistic test environment, a board-typeproduct such as a memory module can be tested on a system-level testsubstrate that provides test conditions that more nearly corresponds toan actual operating environment. For example, the board-type device canbe mounted the motherboard of a computer system which is used as a testsubstrate to test the board-level device under actual operatingconditions. In general, such a board-type product complies with relevantinternational standards such as Joint Electron Device EngineeringCouncil (JEDEC), and the system-level test substrate such as amotherboard of a computer system has a socket for receiving theboard-type product.

[0009] The test substrate used for the actual test is suitable for JEDECstandard memory modules, but not for non-standard memory modules, thatis, custom-made memory modules. For example, when a 200-pin DIMM, whichis a custom-made module for a high-performance server, is mounted on atest substrate for a JEDEC standard 168-pin DIMM used in most desktopcomputers, the memory devices do not operate properly because theoperating environment provided by the test substrate is different fromthe actual operating environment for the 200-pin DIMM.

SUMMARY OF THE INVENTION

[0010] One aspect of the present invention is a system for testing anon-standard memory device under actual operating conditions. The systemcomprises an interface board having a first surface, a second surface,and a pin matching circuit. A socket on the first surface can couple thenon-standard memory device to the pin matching circuit, and the secondsurface is constructed and arranged to couple the pin matching circuitto a standard pin configuration. The second surface of the interfaceboard can be mounted directly on the test substrate. Alternatively, asecond socket on the second surface of the interface board can be usedto couple the pin matching circuit to the test substrate.

[0011] The pin matching circuit can comprise a first matching unit forallowing a one-to-one correspondence between signals of the standard pinconfiguration and non-standard pin configurations. The pin matchingcircuit can further comprise a second matching unit to selectivelyassign signals of the standard pin configuration to signals of thenon-standard pin configuration.

[0012] Another aspect of the present invention is a method for testing amemory device having a non-standard pin configuration under actualoperating conditions comprising. The method comprises coupling thememory device to an interface board that is constructed and arranged toadapt the non-standard pin configuration of the memory device to astandard pin configuration on a test substrate, and operating the testsubstrate.

[0013] A further aspect of the present invention is an interface boardfor an actual test of a non-standard memory device. The interface boardcomprises a circuit board including a first surface, a second surface,and a circuit layer. The interface board further comprises a firstsocket, which is formed on the first surface of the circuit board toreceive the non-standard memory device for electrically connecting thememory devices and the circuit layer. The interface board still furthercomprises a second socket, which is formed on the second surface of thecircuit board, to electrically connect the circuit layer and a standardtest substrate. In particular, the interface board comprises a pinmatching circuit, which is formed in the circuit layer, to match thestandard pin configuration of the test substrate to the non-standard pinconfiguration of the non-standard memory device.

[0014] The pin matching circuit may include a first matching unit and asecond matching unit. The first matching unit allows a one-to-onecorrespondence that uniquely assigns each standard input of controlsignals and address signals of the standard pin configuration to eachnon-standard output of control signals and address signals of thenon-standard pin configuration. The second matching unit allows asequential and interleaving link that selectively assigns each standardinput of data input/output signals of the standard pin configuration toeach non-standard output of data input/output signals of thenon-standard pin configuration.

[0015] The interface board may further comprise a clock invertercircuit, which is formed in the circuit layer to selectively orsimultaneously enable two clock signals of the non-standard pinconfiguration in response to one clock signal of the standard pinconfiguration.

[0016] Another aspect of the present invention is an actual testingsystem for a non-standard memory device. The actual testing systemcomprises a standard test substrate including a plurality of componentsfor providing actual test conditions to the non-standard memory device.The actual testing system further comprises an interface board includinga circuit board, a first and a second sockets, and a pin matchingcircuit. The circuit board has a first surface, a second surface, and acircuit layer. The first socket is formed on the first surface of thecircuit board to receive the non-standard memory device and electricallyconnect the memory device and the circuit layer. The second socket isformed on the second surface of the circuit board to electricallyconnect the circuit layer and a standard test substrate. The pinmatching circuit is formed in the circuit layer to match the standardpin configuration of the standard test substrate with the non-standardpin configuration of the non-standard memory device.

[0017] In the actual testing system, the interface board may furtherinclude a clock inverter circuit, which is formed in the circuit layer,to selectively or simultaneously enable two clock signals of thenon-standard pin configuration in response to one clock signal of thestandard pin configuration.

[0018] The interface board may be mounted on either surface of thestandard test substrate, the surface being, or otherwise opposite to, aplace where the plurality of components are formed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a schematic view showing a conventional process fortesting semiconductor devices.

[0020]FIG. 2 is a cross-sectional view schematically showing anembodiment of a testing system in accordance with the present invention.

[0021]FIG. 3 is an exploded perspective view showing one embodiment ofan interface board in accordance with the present invention.

[0022]FIG. 4 is a block diagram showing an embodiment of a pin matchingcircuit of an interface board in accordance with the present invention.

[0023]FIG. 5 is a block diagram showing an embodiment of a clockinverter circuit of an interface board in accordance with the presentinvention.

[0024]FIG. 6 is a waveform graph showing an output signal of anembodiment of a clock inverter circuit in accordance with the presentinvention.

[0025]FIG. 7 is a plan view showing one exemplary embodiment of a testsubstrate used for the present invention.

[0026]FIG. 8 is a cross-sectional view showing another embodiment of atesting system in accordance with the present invention.

[0027]FIG. 9 illustrates another embodiment of an actual testing systemaccording to the present invention.

DETAILED DESCRIPTION

[0028] Some embodiments of the present invention will now be describedwith reference to the accompanying drawings. The invention may, however,be embodied in many different forms and should not be construed aslimited to the embodiments set forth herein; rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the scope of the invention to those skilled in theart.

[0029]FIG. 2 is a cross-sectional view that schematically illustrates anembodiment of an actual testing system in accordance with the presentinvention. The system of FIG. 2 includes a semiconductor memory device50 to be tested, an interface board 100, and a test substrate 170. In apreferred embodiment, the semiconductor device 50 is a board-typeproduct such as a memory module, and the test substrate 170 correspondsto the motherboard of a computer system. Moreover, the semiconductordevice 50 is a non-standard or custom-made device, whereas the testsubstrate 170 is designed to accommodate a standard device. For example,the semiconductor device 50 is a 200-pin DIMM memory module, and thetest substrate 170 is the motherboard suitable for a 168-pin DIMM memorymodule. The interface board 100, a kind of a test substrate, is designedfor easy mounting and detaching of the semiconductor device 50.

[0030] The interface board 100 is fixed to the test substrate 170 by asupport 150. In addition, the interface board 100 is electricallyconnected to the test substrate 170 via sockets 120 and 140 and aconnection board 130. Other components mounted on the test substrate 170are not depicted in FIG. 2 so as to simplify the drawing for clearillustration of the principles of the present invention.

[0031] The system of FIG. 2 can perform a test of semiconductor device50 under actual operating conditions by mounting the semiconductordevice 50 on the interface board 100, electrically connecting theinterface board 100 to the test substrate 170, and operating the testsubstrate 170. FIG. 2 shows a system designed for creating realistictest conditions for a memory device in a computer motherboard; it is,however, merely one example. Other types of semiconductor devices may betested while mounted on other types of test substrates such asmotherboards of servers, communication equipment and exchangers.

[0032] Referring to FIGS. 2 and 3, the interface board 100 includes acircuit board having a circuit layer. First and a second sockets 110 and120 are formed on first and second surfaces 102 and 104 of the interfaceboard 100, respectively. The second surface 104 faces the test substrate170. Preferably, the interface board 100 is a multi-layered structurehaving, for example, a power plane, a ground plane, at least one signalplane, and insulating layers such as glass fiber layers interposedbetween the planes.

[0033] The first socket 110 receives the semiconductor device 50, andthe second socket 120 receives the connection board 130. The firstsocket 110 has a structure adapted for easy mounting and detaching ofthe semiconductor device 50, and makes an electrical connection betweenthe semiconductor device 50 and the circuit layer of the interface board100. Similarly, the second socket 120 has a structure adapted for easymounting and detaching of the connection board 130, and makes anelectrical connection between the interface board 100 and the testsubstrate 170.

[0034] Preferably, each of the sockets 110 and 120 has flexiblecontact-type pins (not shown), which may have a footprint similar tothat of a dual inline package (DIP). In addition, the first socket 110has a groove 112 in which the contact-type pins are formed and intowhich the semiconductor device 50 can be inserted. Two handles 114 arealso provided at the ends of the groove 112, each being joined by apivot. When the semiconductor device 50 is inserted into the groove 112,the handles 114 are rotated upwardly on the pivot, and the contact-typepins flex to maintain contact with the device 50. Then, by pushing downthe handles 114, the device 50 in the groove 112 can be easily detachedfrom the groove 112. This structure of the socket 110 not only permitseasy detachment of the device 50, but also increases the expected lifespan of the socket 110.

[0035] The first socket 110 has a pin configuration adapted for anon-standard memory module such as a 200-pin DIMM memory module, whereasthe second socket 120 has a pin configuration adapted for a standardmemory module such as a 168-pin DIMM memory module. The 168-pin DIMM iswhat is found in most desktop computers today. At least three memorytypes, FPM, EDO and SDRAM (Synchronous DRAM), are offered in 168-pinDIMMs. Their configurations include 64-bit, 72-bit and 80-bit wide datapaths, with or without ECC (Error Check Code), and they come in 16, 32,64, 128, 256, 512 and 1,024 megabytes sizes.

[0036] In order to test the non-standard memory device 50 under actualoperating conditions, the pin configuration of the non-standard memorydevice 50 should match that of the standard socket, that is, the secondsocket 120. An embodiment of a pin matching circuit for the interfaceboard 100 will be described below. The interface board 100 preferablyincludes further components (not shown) that are verified throughimpedance and signal integrity measurement to create precise testconditions for the device 50 and to eliminate the effect of signal skewor noise. In addition, the interface board 100 is preferably designed tocompensate for environmental clearance between a case where the device50 is directly mounted to the test substrate 170 and a case where thedevice 50 is connected to the test substrate 170 via the sockets 110 and120 and the connection board 130. This environmental compensationincludes adjusting the timing of clock signals, adjusting the timingmargin of control signals, adjusting AC parameters of signals, andadjusting power signals.

[0037] An embodiment of a pin matching circuit according to the presentinvention is shown in FIG. 4. The pin matching circuit 200, which isprovided on the circuit layer of the interface board described above,adapts a non-standard pin configuration 220 (for example, a 200-pinconfiguration) to standard pin configuration 210 (for example a 168-pinconfiguration). The pin matching circuit 200 includes a first matchingunit 202 for control signals and address signals, a second matching unit204 for data input/output (DQ) signals, and a third matching unit 206for power signals (Vcc/GND). In a preferred embodiment, the firstmatching unit 202 allows a one-to-one correspondence that uniquelyassigns each control signal and address signal of the standard pinconfiguration 210 to each control signal and address signal of thenon-standard pin configuration 220. The second matching unit 204preferably allows a sequential and interleaving link that selectivelyassigns each data input/output signal of the standard pin configuration210 to each data input/output signal of the non-standard pinconfiguration 220.

[0038] In an example embodiment for matching a 200-pin output to a168-pin input, the control/address signals include WE (write enable),DQM (data input/output mask), CS (chip select), CLK (system clock), CKE(clock enable), RAS (row address strobe), CAS (column address strobe),SDA (serial data, I/O), SCL (serial clock), SA (address in EEPROM), WP(write protection), A0˜A12 (address) and BA0˜BA1 (bank select address).For example, an input pin No. 27 named WE might correspond to an outputpin No. 148 named WE, and an input pin No. 42 named CLK0 mightcorrespond to an output pin No. 151 named CLK0. On the other hand, DQsignal input pins named DQ0˜DQ63 and CB0˜CB7 (check bit) are linked toDQ signal output pins named DQ0˜DQ71 in a sequential and interleavingorder. For example, the DQ0˜3, DQ4˜7 and DQ8˜11 input pins correspond tothe DQ64˜67, DQ60˜63 and DQ48˜51 output pins, respectively.

[0039] An interface board according to the present invention may furtherinclude a clock inverter circuit. FIG. 5 is a block diagram showing anembodiment of a clock inverter circuit 230, and FIG. 6 is a graphshowing signal waveforms of the clock inverter circuit. The clockinverter circuit 230, which is provided on the circuit layer of theinterface board described above, includes an input terminal 232connected to a CLK0 pin (No. 42 of a 168-pin DIMM), a first outputterminal 234 connected to a CLK0 pin (No. 151 of a 200-pin DIMM), and asecond output terminal 236 connected to a CLK1 pin (No. 150 of a 200-pinDIMM).

[0040] The clock inverter circuit 230 further includes two resistancecircuits 240 and 250 connected in parallel between a positive powerterminal Vdd and a ground terminal Vss. The first resistance circuit 240has a first resistor R1 connected between the power terminal Vdd and afirst node N1, and a second resistor R2 connected between the first nodeN1 and the ground terminal Vss. Similarly, the second resistance circuit250 has a third resistor R1 that is identical to the first resistor andconnected between the power terminal Vdd and a second node N2, and afourth resistor R2 that is identical to the second resistor andconnected between the second node N2 and the ground terminal Vss.Preferably, the first or third resistor R1 is much smaller in value thansecond or fourth resistor R2. For example, R1 can be one hundred ohmswhile R2 is ten kilo-ohms. The first node Ni is connected to both theinput terminal 232 and the first output terminal 234, and the secondnode N2 is connected to the second output terminal 236.

[0041] The clock inverter circuit 230 of FIG. 5 permits tests for aPC100 200-pin device and a PC133 200-pin device. Here, PC100 and PC133refer to 100MHz and 133 MHz data processing speeds, respectively,between the CPU of the computer system (or the test substrate) and thememory module. Other processing speeds can also be accommodated. Whilethe 200-pin PC100 module is constructed to use the system clock signalCLK0 only (in which case CLK1 is not connected (NC)), the 200-pin PC133module utilizes both system clock signals CLK0 and CLK1. The clockinverter circuit 230 keeps CLK1 separate during a test of a 200-pinPC100 module, but simultaneously enables CLK0 and CLK1 during a test ofa 200-pin PC133 module.

[0042] In a case where a power supply voltage of 3.3V is applied to theclock inverter circuit 230, CLK0 of the 168-pin DIMM connected to theinput terminal 232 can be set to a high level or a low level. When CLK0is high, the first node N1 remains high, and therefore, the first outputterminal 234 and CLK0 of the 200-pin DIMM remains high as well. WhenCLK0 of the 168-pin DIMM goes low, CLK0 of the 200-pin DIMM also dropsto the low level because the value of R1 is much lower than R2.

[0043] Since the first and the second resistance circuits 240 and 250have the power terminal Vdd in common, CLK1 of the 200-pin DIMM followsvariations of in the level of CLK0 of the 168-pin DIMM. However, thevariation in CLK1 of the 200-pin DIMM is much smaller than that of CLK0of the 200-pin DIMM because electric charge supplied from the powerterminal Vdd always runs in parallel with the first resistance circuit240, and thus, electric charge flowing in the second resistance circuit250 is limited depending on the voltage level of the first node N1. Thisis confirmed by the waveforms shown in FIG. 6.

[0044]FIG. 7 shows an embodiment of one exemplary test substrate used toprovide an actual operation environment for the present invention. Thetest substrate 170 includes various types of components such as ISAconnectors 262, PCI connectors 264, a PCI audio controller 266, severalline connectors 268, back panel connectors 270, a slot connector 272, aPCI/AGP controller 274, DIMM sockets 276, IDE connectors 278, an LEDconnector 280, a diskette drive connector 282, a power supply connector284, an IDE accelerator 286, a battery 288, an AGP connector 290 andfront panel connectors 292. The components mounted on the test substrate170 are not limited to those illustrated of FIG. 7, and a great varietyof components may be employed for the test substrate 170 depending onthe desired operating conditions for the semiconductor device to betested.

[0045] Another embodiment of an actual testing system is shown in FIG.8. Referring to FIG. 8, the actual testing system 300 has a standardtest substrate 170 on which a plurality of components 310 are mounted.The components 310 provide actual test conditions to the nonstandardmemory device 50. The test substrate 170 has a top surface 302 and abottom surface 304. The top surface 302 receives the interface board 100as well as the components 310. A support 150 fixes the interface board100, on which the memory device 50 is mounted, to the test substrate170. An electrical connection between the memory device 50 and the testsubstrate 170 is made by the first and second sockets 110 and 120 of theinterface board 100, the connection board 130, and the socket 140 of thetest substrate 170.

[0046]FIG. 9 illustrates another embodiment of an actual testing system400. As seen from FIG. 9, other types of components 310 and 320 aremounted on the bottom surface 304 of the test substrate 170, whereas theinterface board 100 is directly mounted on the top surface 302.Therefore, such an arrangement provides enough space to allow easymounting and removal of the interface board 100, simple exchange of thedevice under test, and testing of large numbers of devices.

[0047] The embodiments described herein can be modified in arrangementand detail without departing from the principles of the presentinvention. Accordingly, such changes and modifications are considered tofall within the scope of the following claims.

1. An interface board for testing a non-standard memory device underactual operating conditions comprising: a circuit board including afirst surface, a second surface, and a circuit layer; a first socketformed on the first surface of the circuit board to receive thenon-standard memory device and electrically connect the memory deviceand the circuit layer; a second socket formed on the second surface ofthe circuit board to electrically connect the circuit layer and astandard test substrate; and a pin matching circuit formed in thecircuit layer to match a standard pin configuration of the standard testsubstrate with a non-standard pin configuration of the non-standardmemory device.
 2. The interface board of claim 1, further comprising: aclock inverter circuit formed in the circuit layer to sequentially orselectively enable two clock signals of the non-standard pinconfiguration in response to one clock signal of the standard pinconfiguration.
 3. The interface board of claim 1, wherein the pinmatching circuit includes a first matching unit for allowing aone-to-one correspondence that uniquely assigns each control signal andaddress signal of the standard pin configuration to each control signaland address signal of the non-standard pin configuration.
 4. Theinterface board of claim 3, wherein the pin matching circuit furtherincludes a second matching unit for allowing a sequential andinterleaving link that selectively assigns each data input/output signalof the standard pin configuration to each data input/output signal ofthe non-standard pin configuration.
 5. The interface board of claim 1,wherein the circuit layer has a power plane, a ground plane, and atleast one signal plane that are electrically insulated from each otherand result in a multi-layered structure.
 6. The interface board of claim1, wherein the first socket has a form adequate for a board-type productinto which the non-standard memory device is assembled.
 7. The interfaceboard of claim 1, wherein the first socket includes a groove havingcontact pins for allowing a temporary contact with the non-standardmemory device.
 8. The interface board of claim 2, wherein the clockinverter circuit includes an input terminal connected to a clock signalof the standard pin configuration, first and second output terminalsconnected to first and second clock signals of the non-standard pinconfiguration, respectively, and first and second resistance circuitsconnected in parallel between a power terminal and a ground terminal. 9.The interface board of claim 8, wherein the first resistance circuit hasa first resistor connected between the input terminal and the powerterminal, and a second resistor connected between the input terminal andthe ground terminal, wherein the second resistance circuit has a thirdresistor connected between the second output terminal and the powerterminal, and a fourth resistor connected between the second outputterminal and the ground terminal, and wherein the first output terminalis directly connected to the input terminal.
 10. The interface board ofclaim 9, wherein the first resistor and the third resistor have the samevalue, wherein the second resistor and the fourth resistor have the samevalue, and wherein the first resistor is smaller in value than thesecond resistor.
 11. The interface board of claim 1, wherein thenon-standard memory device is a 200-pin memory module, and wherein thestandard test substrate is a system motherboard for a 168-pin memorymodule.
 12. The interface board of claim 2, wherein only one of theclock signals of the non-standard pin configuration is enabled alonewhen the non-standard memory device is a PC100 device, and wherein twoof the clock signals of the non-standard pin configuration are enabledsimultaneously when the non-standard memory device is a PC133 device.13. A system for testing a non-standard memory device under actualoperating conditions comprising: a standard test substrate comprising aplurality of components for providing actual test conditions to thenon-standard memory device; and an interface board comprising: a circuitboard including a first surface, a second surface, and a circuit layer;a first socket formed on the first surface of the circuit board toreceive the non-standard memory device and electrically connect thememory device and the circuit layer; a second socket formed on thesecond surface of the circuit board to electrically connect the circuitlayer and the standard test substrate; and a pin matching circuit formedin the circuit layer to match a standard pin configuration of thestandard test substrate with a non-standard pin configuration of thenon-standard memory device.
 14. The system of claim 13, wherein theinterface board further comprises a clock inverter circuit formed in thecircuit layer to selectively or simultaneously enable two clock signalsof the non-standard pin configuration in response to one clock signal ofthe standard pin configuration.
 15. The system of claim 13, wherein theinterface board is mounted on a surface of the standard test substratewhere the plurality of components of the standard test substrate areformed.
 16. The system of claim 13, wherein the interface board ismounted on a surface of the standard test substrate opposite to wherethe plurality of components of the standard test substrate are formed.17. The system of claim 13, wherein the pin matching circuit includes afirst matching unit for allowing a one-to-one correspondence thatuniquely assigns each control signal and address signal of the standardpin configuration to each control signal and address signal of thenon-standard pin configuration, and a second matching unit for allowinga sequential and interleaving link that selectively assigns each datainput/output signal of the standard pin configuration to each datainput/output signal of the non-standard pin configuration.
 18. Thesystem of claim 14, wherein the clock inverter circuit includes an inputterminal connected to a clock signal of the standard pin configuration,first and second output terminals connected to first and second clocksignals of the non-standard pin configuration, respectively, and firstand second resistance circuits connected in parallel between a powerterminal and a ground terminal.
 19. The system of claim 18, wherein thefirst resistance circuit has a first resistor connected between theinput terminal and the power terminal, and a second resistor connectedbetween the input terminal and the ground terminal, wherein the secondresistance circuit has a third resistor connected between the secondoutput terminal and the power terminal, and a fourth resistor connectedbetween the second output terminal and the ground terminal, wherein thefirst output terminal is directly connected to the input terminal,wherein the first resistor and the third resistor have the same value,wherein the second resistor and the fourth resistor have the same value,and wherein the first resistor is smaller in value than the secondresistor.
 20. The system of claim 13, wherein the non-standard memorydevice is a 200-pin memory module, and wherein the standard testsubstrate is a system motherboard for a 168-pin memory module.
 21. Asystem for testing a non-standard memory device under actual operatingconditions comprising: an interface board having a first surface, asecond surface, and a pin matching circuit; and a socket on the firstsurface to couple the non-standard memory device to the pin matchingcircuit; wherein the second surface is constructed and arranged tocouple the pin matching circuit to a standard pin configuration.
 22. Asystem according to claim 21 further comprising a test substratedirectly mounted to the second surface of the interface board.
 23. Asystem according to claim 21 wherein the socket is a first socket, andfurther comprising a second socket on the second surface of theinterface board to couple the pin matching circuit to a test substrate.24. A system according to claim 23 further comprising a test substratecoupled to the second socket.
 25. A system according to claim 23 furthercomprising a connection board coupled between the second socket and thetest substrate.
 26. A system according to claim 25 wherein the testsubstrate comprises a third socket constructed and arranged to receivethe connection board.
 27. A system according to claim 24 furthercomprising a support constructed and arranged to affix the interfaceboard to the test substrate.
 28. A system according to claim 21 whereinthe interface board further comprises a clock inverter circuit to drivetwo clock signals of the non-standard pin configuration in response toone clock signal of the standard pin configuration.
 29. A systemaccording to claim 21 wherein the pin matching circuit comprises a firstmatching unit for allowing a one-to-one correspondence between signalsof the standard pin configuration and non-standard pin configurations.30. A system according to claim 29 wherein the pin matching circuitfurther comprises a second matching unit to selectively assign signalsof the standard pin configuration to signals of the non-standard pinconfiguration.
 31. A method for testing a memory device having anon-standard pin configuration under actual operating conditionscomprising: coupling the memory device to an interface board that isconstructed and arranged to adapt the non-standard pin configuration ofthe memory device to a standard pin configuration on a test substrate;and operating the test substrate.
 32. A method according to claim 31wherein coupling the memory device to the interface board comprisescoupling the memory device to a socket on a first surface of theinterface board.
 33. A method according to claim 32 wherein theinterface board comprises: a pin matching circuit coupled to the socket;and a second surface that is constructed and arranged to couple the pinmatching circuit to the standard pin configuration on the testsubstrate.
 34. A method according to claim 31 wherein the interfaceboard is coupled to the test substrate by a connection board.
 35. Amethod according to claim 31 wherein the interface board is directlymounted to the test substrate.